1. Technical Field
Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a resistive memory device, an operating method thereof and a system having the same.
2. Related Art
There has been an increasing demand for a memory device which has nonvolatile properties while repetitively performing a read/write operation, and research has been continuously conducted on the memory device.
As a result of the research, a resistive memory device has emerged.
Among a variety of resistive memory devices, a phase change memory device includes a resistance element for storing data and an access element. When the access element is driven through a word line to write data, a write current may be applied to the resistance element from a bit line to change the resistance state of the resistance element into a crystal state (low resistance state) or amorphous state (high resistance state).
The resistance of a phase change material forming the resistance element is increased by various reasons. This is referred to as resistance drift.
More specifically, although a memory cell programmed within a target range of a resistance state, the resistance value of the memory cell gradually increases with time due to resistance drift. Then after a certain time passes, the resistance value of the memory cell may exceed the target resistance range to reach the resistance range of another state. At this time, the memory cell may lose data stored therein, and the length of time that the memory cell may retain the data is referred to as a retention time. When the retention time is too short, a stable operation of the memory device may not be guaranteed.
FIG. 1 is a diagram for explaining resistance drift of resistive memory cells over time.
In general, a resistive memory device writes desired data in a memory cell through a program and verify operation. The program and verify operation indicates an operation of programming data to a memory cell and verifying the programmed data, which is repeated until the resistance value of the memory cell falls within a target range of a resistance state.
FIG. 1 illustrates a case in which memory cells are programmed to have a resistance state R1 or R2 and a verify read operation is performed after about 125 ns. Referring to FIG. 1, it can be seen that the resistances of the memory cells within the target range of the resistance state R1 or R2 increase with time. In particular, resistance drift significantly occurs in the memory cells programmed to have the high resistance state R2.
As the time passes, the resistances of the memory cells programmed to have the resistance state R1 continuously increase. When the resistances of the memory cells exceed reference resistance Ref, the data of the memory cells may not be distinguished by the reference resistance Ref, even though the data were written as the resistance state R1.
FIGS. 2A and 2B are diagrams for explaining resistance drift of resistive memory cells.
FIG. 2A illustrates resistance changes with the passage of time, and FIG. 2B illustrates voltage changes with the passage of time.
Referring to FIGS. 2A and 2B, it can be seen that resistance is significantly changed immediately after data are written in the memory cells as a resistance state R1 or R2. As such, it is known that the resistance change caused by resistance drift is exponentially proportional to time as expressed by Equation 1 below.R(t)=R(t0)(t/t0)v  [Equation 1]
Here, t0 represents the amount of time elapsed from completion of a write operation to the initial read operation, R(t0) represents an initial resistance value, v represents a drift coefficient, and t represents the time interval until a resistance value of a resistance element is read after the time t0.
Thus, during a write operation based on the program and verify method, a verify read operation is performed immediately after a program operation, in order to determine a pass or fail of the program operation for a corresponding memory cell. Even though the write operation is completed, the magnitude of the resistance rapidly increases within a very short time, and the time elapsed until reaching a resistance region of another state becomes very short. That is, the retention time of the memory cell inevitably decreases.
A memory cell configured to store two or more-bit data is referred to as a multi-level cell (MLC). Memory devices have been configured with MLCs, in order to increase the capacity of the memory devices.
In order to increase the retention time, a difference between reference resistance values for determining the respective resistance states may be set as a large value. However, when the difference between the reference resistance values is increased, there are difficulties in implementing MLCs capable of storing three or more bits of data. Thus, a method for reducing resistance drift is in demand to implement stable MLCs.